How To Read 32 Bit Values To To The Command Registers

STM32duino GPIO Registers and Programming

Chip Setting in C

Setting a flake

Use the bitwise OR operator ( | ) to set a bit.

That will set bit 10.

Clearing a flake

Utilise the bitwise AND operator (&) to clear a bit.

That will clear flake x. You lot must invert the bit cord with the bitwise Not operator (~), and so AND it.

Toggling a bit

The XOR operator (^) can be used to toggle a bit.

That will toggle scrap x.

Checking a bit

To check a bit, shift the number ten to the right, and so bitwise AND it:

That will put the value of bit 10 into the variable scrap.

Changing the nth bit to 10

Setting the nth bit to either 1 or 0 tin can be achieved with the post-obit:

number ^= (-10 ^ number) & (1              << n);

Bit n will be gear up if x is 1, and cleared if x is 0.

GPIO Registers

The libmaple libraries, on which STM32duino is based, provides access to registers by the syntax:

where REG can be one of the following:

CRH and CRL

CRH is used to set up type/and or speed of pins 8-fifteen of the port.
CRL is used to set type/and or speed of pins 0-7 of the port.
Accessed as a 32 bit word, with 4 bits representing the state of each pin. Out of these iv bits, the low two bits are MODE, and high 2 bits are CNF.

The four bits for each pivot tin can be set to:
0b0011 (binary) or 0x3 (HEX) - Corresponds to setting pin as output, same as pinMode()
0b1000 or 0x8 - Corresponds to setting pin every bit input, same as pinMode()

Say I want to set PORTA pins 0, 3 and 4 to OUTPUT and 1, half-dozen, 7 to INPUT, and leave pins 2 and v in their original state. The code is:

PORTA->regs->CRL = (PORTA->regs->CRL &              0x00F00F00) |              0x88000080              |0x00033003;                              //0x00F00F00 is bitmask to retain value of pins two and v in original country                              //0x88000080 is bitmask to ready inputs                              //0x00033003 is bitmask to set outputs            

IDR - Input Data Register

Used to read input of entire xvi pins of port at once. Accessed as a 32 bit word whose lower 16 bits correspond each pin. The pins being read must be set to INPUT mode past using CRL/CRH or pinMode() earlier using this.

Say I desire to read pins A2. The code is:

              bool              effect = GPIOA->regs->IDR &              0x0004;                              //returns true if A2 is High                              //0x0004 is 0b0000000000000100            

ODR - Output Data Register

Used to write output to entire 16 pins of port at once. Accessed and written as a 32 bit word whose lower xvi bits correspond each pin. The pins existence read must be set to OUTPUT way by using CRL/CRH or pinMode() earlier using this.

Say I want to set pins A2, A12 and A13, and reset (clear) all other pins in the 16 pivot charabanc. The code is:

GPIOA->regs->ODR =              0b0011000000000100;                              //notation,  binary            

Now if I desire to set and clear A2, A12 and A13 without altering other pins, the code is:

                              //Set A2, A12, A13 (HIGH)              GPIOA->regs->ODR |=              0b0011000000000100;                              //Articulate A2, A12, A13 (LOW)              GPIOA->regs->ODR &= ~(0b0011000000000100);

merely find how, if we want to impact only some pins, we have to READ, MASK and WRITE. That's why there is BRR and BSRR

BRR - Bit Reset Register

32 bit word. Lower xvi bits have 1'south where bits are to be set to "LOW". Upper xvi bits take i's where bits are to be set "HIGH". 0'due south hateful ignore

At present, to set and clear A2, A12, A13 while preserving the land of all other pins in the port, the code is:

                              //Set A2, A12, A13 (Loftier)              GPIOA->regs->BRR =              0b0011000000000100              <<              xvi;                              //movement to upper 16 bits                              //Clear A2, A12, A13 (Depression)              GPIOA->regs->BRR =              0b0011000000000100;

BSRR - Bit Ready Reset Register

BSRR is like the complement of BRR. It's also a 32 bit give-and-take. Lower 16 bits have 1's where $.25 are to be set to "High". Upper sixteen $.25 have ane's where $.25 are to exist prepare "Low". 0's mean ignore

In this case, to set and articulate A2, A12, A13 while preserving the country of all other pins in the port, the code is:

                              //Fix A2, A12, A13 (HIGH)              GPIOA->regs->BSRR =              0b0011000000000100;                              //Clear A2, A12, A13 (Low)              GPIOA->regs->BSRR =              0b0011000000000100              <<              sixteen;                              //movement to upper xvi bits            

Combination of BRR and BSRR

Since BRR and BSRR are opposite of each other, you can utilise both if you don't want to practise the bit shift left functioning .

In this case, to prepare and articulate A2, A12, A13 while preserving the state of all other pins in the port, the code is:

                              //Set A2, A12, A13 (HIGH)              GPIOA->regs->BSRR =              0b0011000000000100;                              //lower 16 $.25                              //Clear A2, A12, A13 (Depression)              GPIOA->regs->BRR =              0b0011000000000100;                              //lower 16 bits            

Sources:

• http://embedded-lab.com/blog/stm32-gpio-ports-insights/
• http://hertaville.com/stm32f0-gpio-tutorial-part-1.html
• http://stackoverflow.com/questions/47981/how-practice-you-set-clear-and-toggle-a-single-flake-in-c-c?rq=1
• https://gist.github.com/iwalpola/6c36c9573fd322a268ce890a118571ca

How To Read 32 Bit Values To To The Command Registers,

Source: https://gist.github.com/e35f1ff1485d660edf365241dacfa387

Posted by: morganforway.blogspot.com

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